The present invention relates to a non-volatile semiconductor memory, and more specifically, to a layout of a column selector of the non-volatile semiconductor memory having a double (two-layered) bit line structure for use in e.g., a flash EEPROM (electrically erasable programmable read-only memory).
In the semiconductor memory, in most cases, a word line and a bit line are divided in order to attain a high-speed read-out operation.
Particularly in a flash EEPROM, when a data rewrite operation to a certain memory cell is performed, other memory cells which share the same bit line or word line with the target memory cell, are placed in a semi-selection state, with the result that data stored in the other memory cells are altered. This phenomenon is called "disturbance during a data-rewrite mode". To prevent such a phenomenon, a memory cell array is divided into a plurality of blocks (cell-blocks) so that the word lines and bit lines of a block to be subjected to an erase operation can be electrically isolated from those of another block.
Generally, each cell block is constructed so as to have 512K bits (64K bites) constituting 1K word line.times.512 bit lines or 512 word lines.times.1 bit line. A row decoder and a column decoder are respectively divided into a plurality of row sub decoders and a plurality of column sub selectors, corresponding to a plurality of cell blocks.
Now, we will explain a column decoder of a conventional flash EEPROM.
In the flash EEPROM, the column selector, to which a selection signal is supplied from the column decoder, is constituted of a plurality of column sub-selectors which are arranged in every cell block of 512 K bits. The column sub-selectors are arranged in a discrete form. Size of a memory chip is influenced by the manner how to arrange wiring layers between the column sub-selectors. Furthermore, if a memory capacity increase, the number of cell blocks is inevitably increased, resulting in an increase of wiring resistance between column sub-selectors. To prevent such an increase in wiring resistance, a double-layer metal wiring (generally, aluminum wiring) has been generally employed as the wiring layer between the column sub-selectors.
FIG. 5 shows an equivalent circuit of part of a conventional NOR-type flash EEPROM employing a double bit line architecture which consists of double-layered aluminium wiring layers formed in a column direction of the memory cell array.
In FIG. 5, a plurality of cell blocks 51.sub.i (i=1 to n) are arranged in a column direction of a memory cell array. In each of the cell blocks 51.sub.i, a plurality of cell transistors CTs constituting 512K bits are arranged in a matrix form.
In each of the cell block 51.sub.i, sub-word lines SWLs are arranged in a row direction. To each of the sub word lines, control gates of the cell transistors CTs belonging to the corresponding row are connected in common. Sub-bit lines SBLs are arranged in individual columns in the column direction. To each of the sub-bit lines, drains of the cell transistors CTs belonging to the corresponding row, are connected in common. To sources of the cell transistors CTs within each of the cell blocks 51.sub.i, a common block source line BSL is connected.
Main bit lines MBLs are extended in the column direction of the memory cell array. To each of the main bit lines MBLs, sub lit lines corresponding to a plurality of cell blocks 51.sub.1 to 51.sub.n are connected in common.
Each of the column sub-selectors 52.sub.i (i=1 to n) is extended at one side of the corresponding cell block 51.sub.i in the column direction (vertical direction in FIG. 5). In each column sub-selector 52.sub.i, a plurality of block selection transistors (bit line selection transistor) (BSTs) are arranged in the row direction for selecting the corresponding sub-bit lines SBLs of the cell block 51.sub.i.
In the column sub-selector 52.sub.i, each of a plurality of block selection transistors BSTs is connected between the sub bit line SBL of the corresponding cell block 51.sub.i and the corresponding main bit line MBL. Further, a block decode line BDL is extended in the row direction. To the block decode line BDL, the transistor BST gates are connected in common.
The main bit lines MBLs are collectively connected at each of one end thereof via the corresponding Y selection transistor (column selection transistor) CST. The main bit lines MBLs thus connected are further connected to a write load transistor (not shown), a sense-amplifier (not shown) and the like.
The column selection transistors CSTs are independently driven by a main column decoder (not shown). The block decode lines BDLs are independently driven by a block decoder and a column sub-decoder (not shown). The sub word lines SWLs are independently driven by a column sub-decoder (not shown). The block source line (BSL) is set so as to have a predetermined potential by a block source decoder (not shown) in accordance with an operation mode.
With the aforementioned construction, the sub bit lines arranged in every cell block are electrically isolated from those of other cell block by each of the column sub-selectors 52.sub.i.
In the aforementioned example, a single main bit line is arranged per single sub bit line. However, in some cases, a single main bit line is arranged per a plurality of sub bit lines. Furthermore in the aforementioned example, a plurality of column sub-selectors is arranged in parallel per single main bit line. In some cases, a single column sub-selector may be connected to a single main bit line.
FIG. 6 is an example of a practically and conventionally used pattern layout surrounding a column sub-selector 52.sub.1 for attaining the circuit shown in FIG. 5. More specifically, the figure shows a pattern layout having a single main bit line MBL and two sub bit lines SBLs (the single main bit line is formed in the midway of both two sub-bit lines, in parallel).
In FIG. 6, in a column sub-selector region, there are two block decode lines BDLs, a block source line BSL, a transistor active region SDG, a plurality of sub-bit lines SBLs, a main bit line MBL, and a plurality of gate wiring layer GLs. The two block decode lines BDLs are made of a first aluminium wiring layer and arranged in parallel to each other in a row direction. The block source line BSL is made of the first aluminum wiring layer and arranged in the row direction. The transistor active region SDG is formed selectively on a surface portion of a semiconductor substrate (alternatively a semiconductor layer or a well region) so as to extend in the row direction. The sub-bit lines SBLs are made of the first aluminium wiring layer and arranged in parallel to each other in a column direction. The main bit line MBL is made of a second aluminium wiring layer and arranged in parallel to the sub-bit line in the column direction. The gate wiring layers GLs are made of a polysilicon wiring layer and arranged in the column direction.
In this layout, a single active region SDG is constituted of adjacent two block selection transistors BSTs. The adjacent two block selection transistors BSTs share a common drain region. In addition, the sub-bit lines SBLs are extended in the column direction from above the corresponding source regions of the active regions SDGs. Each of the source regions is connected to the sub-bit line SBL at a contact portion 53.
Furthermore, the main bit line MBL is extended from above the common drain region of the active regions SDGs in the column direction. The main bit line MBL is connected to the common drain region by way of a connection line 54. More specifically, the connection line 54 is made of the first aluminium wiring layer and arranged above the common drain region. The common drain region and the connection line 54 are connected with each other at a contact portion 55. The connection line 54 is connected to the main bit line MBL through a via hole (through hole) 56.
The gate wiring layers GL are formed so as to extend in the column direction above channel regions formed between the source region and the common drain region of the active region SDG. One end of each of two gate wiring layers GLs corresponding to adjacent two block selection transistors BST is connected to the corresponding line of the two block decode lines BDLs via the corresponding contact portion 57.
When a single column sub-selector having the aforementioned pattern layout and a single column sub-selector having a symmetric pattern layout are arranged side by side in the column direction, it is possible to share the main bit line with two sub bit lines of each of the two column sub-selectors (in total, four sub-bit lines).
The pattern layout for use in the aforementioned conventional column sub-selector including the peripheral portion thereof is effective in the case where the pattern constituted of utmost 4 sub bit lines and a single main bit line, is repeated, and the active regions SDGs each having two transistors are arranged within one pitch width in the pattern.
However, when a device is miniaturized more and scale-down of the memory cell pitch is advanced, with the result that the interval between the bit lines is reduced, if the aforementioned conventional pattern-layout is used, the active regions corresponding to the two block selection transistors sometimes cannot be set within one pitch. In this case, it is necessary to modify the pattern layout in such a manner that a pattern having a single main bit line and 4 or 8 sub bit lines is repeated.
The reduction of the memory cell pitch due to the miniaturization of the device may also require, for example, a more effective or improved element isolation process. In this case, if a LOCOS process using a conventional selective oxidation film is changed to an STI (shallow Trench Isolation) process using a buried insulating-film, the depth of the source/drain can be regarded as the source/drain interval. As a result, the source/drain interval in a plane direction is significantly reduced.
In contrast, in the block selection transistor BST shown in FIG. 5, even if the device isolation process is changed, there is no factor to reduce the planar source/drain interval. Consequently, the margin for the pattern layout of the column sub-selector is inevitably reduced. It follows that the pattern layout must be modified so as to repeat a pattern constituted of a single main bit line and 4 or 8 sub bit lines.
When the pattern layout of the column sub-selector shown in FIG. 6 is viewed from the aforementioned points, in the regions where two block decode lines BDLs are arranged and where a block source line BSL of the first aluminium wiring is arranged, only wiring is present. These regions appear to be a complete dead-space in consideration of device arrangement. If a larger number of block decode lines is used for circuit design, the dead space is further enlarged.
The enlargement of the dead space in the memory such an NOR-type flash EEPROM whose cell-block bit capacity is defined by the standard, induces an increase of a pattern area of the column sub-selector, compared to the memory of a previous generation. Hence, if the aforementioned pattern is continuously used even though the device is miniaturized, a rate of the area occupied by the memory cell in the pattern will decrease.
In the meantime, in the conventional EEPROM, the device is designed in such a manner that transistors to be arranged around a row decoder and a column decoder (to which a high voltage Vpp (about 10V) is applied at a write/erase mode) have a junction resistance voltage of Vpp (about 10V) or more.
Particularly, in the flash memory where a negative voltage is applied to a word line at an erase operation, NMOS transistors constituting the row decoder and the column decoder, are usually formed within a p-well region formed on an n-well region of a p-type semiconductor substrate. In this case, the junction resistance voltage and the punch-through voltage of the NMOS transistors are usually set at Vpp or more.
However, if the aforementioned device structure of the NMOS transistor formed within the p-well region on the n-well region is directly employed as a device structure of the block selection transistor of the column selector, the following problems may arise.
(1) Increase of pattern layout area
In consideration of an alignment error of a mask pattern and the depth of a well region, any one of the block selection transistor, the boundary of the p-well region/n-well region, and the pattern layout of the cell transistor is arranged with a sufficient margin to form devices having uniform characteristics. However, it is not preferable to give a sufficient margin since the dead space between the column sub-selector and the cell block is increased due to the margin.
(2) Overspec of resistant voltage on device design
If the block selection transistor is designed so as to have a resistant voltage of Vpp (about 10V) or more, the following structural problems which prevent scale-down of the device are caused.
(a) A dose amount of the ion implantation performed to prevent the field-inversion of the NMOS region must be reduced in order to ensure the junction resistance voltage of Vpp (about 10V) or more of the block selection transistor.
As a result, the interval between the n+drain region/n+ source region of the block selection transistor must be larger than that of the cell transistor. This is a serious matter when the pattern layout shown in FIG. 6 is employed.
(b) To ensure the punch-through resistance voltage of the block selection transistor at Vpp (about 10V) or more, its channel dope concentration must be increased. As a result, a vias effect of a substrate increases and the characteristics of a selected transistor come to deteriorate.
In particular, when a voltage of about 5V is applied to the source of a write load transistor (not shown) connected to one end of the column selection transistor CST shown in FIG. 5, it is not preferable that the threshold voltage of the block selection transistor BSL due to the substrate vias effect is large, since the large threshold voltage degrades characteristics of the block selection transistor.
As mentioned above, in a conventional non-volatile semiconductor memory employing a double bit line architecture, it is necessary to modify the pattern layout surrounding the column sub-selector, with the miniaturization of the device and reduction of the memory cell pitch.
Furthermore, if the device structure of each of the transistors arranged surrounding the decoder and its peripheral portion, the transistors being designed so as to have a junction resistance voltage and a punch-through voltage of at least Vpp (10V) (the voltage applied at the write operation in the non-volatile semiconductor memory), is directly employed as a device structure of the block selection transistor of the column sub-selector, various problems are produced.